/data/project/t2023/ssn_ref/gpio_t/tsdb_outdir/dft_inserted_designs/gpio_t_rtl1.dft_inserted_design/modified_rtl_files/gpio_t.v
/data/project/t2023/ssn_ref/gpio_t/tsdb_outdir/instruments/gpio_t_rtl1_bscan.instrument/gpio_t_rtl1_tessent_bscan_cells.v
/data/project/t2023/ssn_ref/gpio_t/tsdb_outdir/instruments/gpio_t_rtl1_bscan.instrument/gpio_t_rtl1_tessent_bscan_interface.v
/data/project/t2023/ssn_ref/gpio_t/tsdb_outdir/instruments/gpio_t_rtl1_bscan.instrument/gpio_t_rtl1_tessent_bscan_logical_group_DEF.v
/data/project/t2023/ssn_ref/library/pad_cells/iopad.v
/data/project/t2023/ssn_ref/library/pad_cells/iopad_sel.v
/data/project/t2023/ssn_ref/library/standard_cells/verilog/adk.v
/data/project/t2023/ssn_ref/top_bscan/1.insert_bscan/simulation_outdir/chip_top_rtl1.simulation_signoff/JtagBscanPatterns.simulation/patterns.configuration
/data/project/t2023/ssn_ref/top_bscan/1.insert_bscan/simulation_outdir/chip_top_rtl1.simulation_signoff/JtagBscanPatterns.simulation/patterns_directory/JtagBscanPatterns.v
/data/project/t2023/ssn_ref/top_bscan/tsdb_outdir/dft_inserted_designs/chip_top_rtl1.dft_inserted_design/modified_rtl_files/chip_top.v
/data/project/t2023/ssn_ref/top_bscan/tsdb_outdir/instruments/chip_top_rtl1_bscan.instrument/chip_top_rtl1_tessent_bscan_interface.v
/data/project/t2023/ssn_ref/top_bscan/tsdb_outdir/instruments/chip_top_rtl1_bscan.instrument/chip_top_rtl1_tessent_bscan_logical_group_DEF.v
/data/project/t2023/ssn_ref/top_bscan/tsdb_outdir/instruments/chip_top_rtl1_ijtag.instrument/chip_top_rtl1_tessent_sib_1.v
/data/project/t2023/ssn_ref/top_bscan/tsdb_outdir/instruments/chip_top_rtl1_ijtag.instrument/chip_top_rtl1_tessent_sib_2.v
/data/project/t2023/ssn_ref/top_bscan/tsdb_outdir/instruments/chip_top_rtl1_ijtag.instrument/chip_top_rtl1_tessent_tap_main.v
/data/project/t2023/ssn_ref/top_bscan/tsdb_outdir/instruments/chip_top_rtl1_ijtag.instrument/chip_top_rtl1_tessent_tdr_bsconfig.v
