#! /bin/sh
#\
exec tessent -shell -log logfiles/$0.log -replace -dofile "$0" -arguments ${1+"$@"}

# Set the context to insert DFT into top-level design
set_context dft -rtl -design_id rtl1

# Set the location of the TSDB. Default is the current working directory.
set_tsdb_output_directory ../tsdb_outdir
# open_tsdb ../../cphy/tsdb_outdir
# open_tsdb ../../cphy_t/tsdb_outdir
open_tsdb ../../gpio_t/tsdb_outdir
# open_tsdb ../../gpio_i_t/tsdb_outdir

# Open the TSDB of all the child cores
# open_tsdb ../../wrapped_cores/processor_core/tsdb_outdir
# open_tsdb ../../wrapped_cores/gps_baseband/tsdb_outdir

# Read the tessent cell library
read_cell_library ../../library/standard_cells/tessent/adk.tcelllib

# Read hard_macros
read_verilog ../../library/plls/pll.v -blackbox -exclude_from_file_dictionary

# Read the design view of chip_top
set_design_sources -format verilog -y ../../library/pad_cells -extension v
read_verilog ../rtl/chip_top.v
read_verilog ../rtl/rds_process.v
set_current_design chip_top

set_design_level chip

# Define set_dft_specification_requirements to insert boundary scan at chip-level
# Set memory_test on even if there is not memories at the top level so that the memory 
# clock DRCs are run outside the memory inserted blocks.
set_dft_specification_requirements -boundary_scan on -memory_test on

# Toggle the enable to relock the PLL
# add_dft_control_points PLL_1/enable -dft_signal_source_name all_test

# Specify the TAP pins using set_attribute_value
set_attribute_value TCK  -name function -value tck
set_attribute_value TDI  -name function -value tdi
set_attribute_value TMS  -name function -value tms
set_attribute_value TRST -name function -value trst
set_attribute_value TDO  -name function -value tdo


# register_static_dft_signal_names bs_cphy_t0_bypass 
# add_dft_signals bs_cphy_t0_bypass -create_with_tdr


check_design_rules

# Create and report a DFT Specification
set spec [create_dft_specification -sri_sib_list {bsconfig}]

report_config_data $spec

read_config_data -in [get_config_elements Tap(main) -hierarchical] -last -from_string {
    DeviceIDRegister {
       manufacturer_id_code: 11'b1011; //'
    }
}

read_config_data -in [get_config_elements Tap(main)/HostBscan -hierarchical] -last -from_string {
    InstructionCodes {
      CLAMP              : 4'b0001;
      EXTEST             : 4'b0010;
      EXTEST_PULSE       : 4'b0011;
      EXTEST_TRAIN       : 4'b0100;
      INTEST             : 4'b0101;
      SAMPLE_PRELOAD     : 4'b0110;
      HIGHZ              : 4'b0111;
    }
}
set_config_value -in [get_config_elements HostIjtag(1) -hierarchical] instruction_codes 4'b1101;
set_config_value -in [get_config_elements Tap(main)/DeviceIDRegister -hierarchical] instruction_codes 4'b1110;
set_config_value -in [get_config_elements Tap(main) -hierarchical] bypass_instruction_codes 4'b1111;

read_config_data -in [get_config_elements Sib(bsconfig) -hierarchical] -last -from_string {
    Tdr(bsconfig) {
        length: 32;
        DataOutPorts {
          connection(0)    : d0nt_buf0/A;
        }
    }
}

# Segment the boundary scan to be used during logic test
set_config_value $spec/BoundaryScan/max_segment_length_for_logictest  80

# Add auxiliary mux on the inputs and outputs used for SSN bus and bus_clock
# bus_in {GPIO3_0 GPIO3_1} bus_out {GPIO4_0 GPIO4_1}  bus_clock {GPIO3_2}
read_config_data -in ${spec}/BoundaryScan -from_string {
  AuxiliaryInputOutputPorts {
    // auxiliary_input_ports   : GPIO3_0, GPIO3_1, GPIO3_2;
    // auxiliary_output_ports  : GPIO4_0, GPIO4_1 ;
  }
  UserInstructions {
      UserInstruction(selx) {
        tap_host_scan_interface_id  : Tap(main)/HostIjtag(1);
        // instruction_codes           : 4'b1001; // '
        bsdl_visibility             : public ;
        user_register               : selx[32] ; 
        capture_value               : 32'b0; // '
      }
  }
}

# set_config_value $spec/BoundaryScan/pin_order_file ./chip_top.pinorder                  

read_config_data -in ${spec}/BoundaryScan -last -from_string {
}

report_config_data $spec

# Generate and insert the hardware
process_dft_specification 

# Extract IJAG network and create ICL file for the design
extract_icl -create_ijtag_graybox on
write_design_import_script chip_top.dc_design_load_script1 -use_relative_path_to ../1.insert_bscan -replace

# Create patterns(testbenches) to verify the inserted DFT logic
source ./a.pdl
set spec [create_patterns_specification]
report_config_data $spec

process_pattern_specification

# Point to the libraries and run simultion
set_simulation_library_sources -v ../../library/standard_cells/verilog/*.v \
                               -y ../../library/plls \
                               -y ../../library/memories \
                               -extension v

#run_testbench_simulations
run_testbench_simulations -simulator vcs \
        -compilation_options "-kdb +define+debussy +incdir+/data/project/t2023/ssn_ref/wrapped_cores/processor_core/rtl" \
        -simulator_options "-kdb -debug_access+all"

exit
