#! /bin/sh
#\
exec tessent -shell -log logfiles/$0.log -replace -dofile "$0" -arguments ${1+"$@"}

# Set the context to insert DFT into top-level design
set_context dft -rtl -design_id rtl2

# Set the location of the TSDB. Default is the current working directory.
set_tsdb_output_directory ../tsdb_outdir
# open_tsdb ../../cphy/tsdb_outdir
# open_tsdb ../../cphy_t/tsdb_outdir
open_tsdb ../../gpio_t/tsdb_outdir
# open_tsdb ../../gpio_i_t/tsdb_outdir

# Open the TSDB of all the child cores
# open_tsdb ../../wrapped_cores/processor_core/tsdb_outdir
# open_tsdb ../../wrapped_cores/gps_baseband/tsdb_outdir

# Read the tessent cell library
read_cell_library ../../library/standard_cells/tessent/adk.tcelllib

# Read hard_macros
read_verilog ../../library/plls/pll.v -blackbox -exclude_from_file_dictionary

# Read the design view of chip_top
set_design_sources -format verilog -y ../../library/pad_cells -extension v
read_verilog ../rtl/rds_process.v


read_verilog ../tsdb_outdir/instruments/chip_top_rtl1_ijtag.instrument/chip_top_rtl1_tessent_tap_main.v
read_verilog ../tsdb_outdir/instruments/chip_top_rtl1_ijtag.instrument/chip_top_rtl1_tessent_tdr_bsconfig.v
read_verilog ../tsdb_outdir/instruments/chip_top_rtl1_ijtag.instrument/chip_top_rtl1_tessent_sib_1.v
read_verilog ../tsdb_outdir/instruments/chip_top_rtl1_ijtag.instrument/chip_top_rtl1_tessent_sib_2.v
read_verilog ../tsdb_outdir/instruments/chip_top_rtl1_bscan.instrument/chip_top_rtl1_tessent_bscan_logical_group_DEF.v
read_verilog ../tsdb_outdir/instruments/chip_top_rtl1_bscan.instrument/chip_top_rtl1_tessent_bscan_interface.v
read_verilog ../tsdb_outdir/dft_inserted_designs/chip_top_rtl1.dft_inserted_design/modified_rtl_files/chip_top.v



set_current_design chip_top

set_design_level chip

# Define set_dft_specification_requirements to insert boundary scan at chip-level
# Set memory_test on even if there is not memories at the top level so that the memory 
# clock DRCs are run outside the memory inserted blocks.
set_dft_specification_requirements -bsdl_extraction on

# Toggle the enable to relock the PLL
# add_dft_control_points PLL_1/enable -dft_signal_source_name all_test

# Specify the TAP pins using set_attribute_value
set_attribute_value TCK  -name function -value tck
set_attribute_value TDI  -name function -value tdi
set_attribute_value TMS  -name function -value tms
set_attribute_value TRST -name function -value trst
set_attribute_value TDO  -name function -value tdo

# Specify all clocks so that the proper BSCAN cells gets inserted automatically for them
# add_clocks PLL_1/pll_clock_0 -reference REF_CLK -freq_multiplier 16
# add_clock REF_CLK -period 48ns
# add_clock INCLK  -period 10ns

# add_primary_inputs [get_pins cphy_t0/bs_bypass]
# add_input_constraints [get_pins cphy_t0/bs_bypass] -C1
# 
# set_attribute_value [get_pins cphy_t0/BS_BYPASS_PORT] -name unused_tcd_bscan_external_port -value yes

write_design -tsdb

set_dft_specification_requirements -bsdl_extraction on
check_design_rules

exit
