#! /bin/sh
#\
exec tessent -shell -log logfiles/$0.log -replace -dofile "$0" -arguments ${1+"$@"}

# Set the context to insert DFT into top-level design
set_context dft -rtl -design_id rtl1

# Set the location of the TSDB. Default is the current working directory.
set_tsdb_output_directory ../tsdb_outdir

# Open the TSDB of all the child cores

# Read the tessent cell library
read_cell_library ../../library/standard_cells/tessent/adk.tcelllib

# Read hard_macros
read_verilog ../../library/plls/pll.v -blackbox -exclude_from_file_dictionary

# Read the design view of chip_top
set_design_sources -format verilog -y ../../library/pad_cells -extension v
read_verilog ../rtl/gpio_t.v
set_current_design gpio_t

set_design_level physical_block

# Define set_dft_specification_requirements to insert boundary scan at chip-level
# Set memory_test on even if there is not memories at the top level so that the memory 
# clock DRCs are run outside the memory inserted blocks.
set_dft_specification_requirements -boundary_scan on -memory_test on

set_boundary_scan_port_options -pad_io_ports {PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7}

check_design_rules

# Create and report a DFT Specification
set spec [create_dft_specification]

report_config_data $spec

# read_config_data -in ${spec}/IjtagNetwork/HostScanInterface(tap)/Tap(main)/HostIjtag(1)/Sib(sri) -last -from_string {
#     Tdr(bsconfig) {
#         length: 32;
#         DataOutPorts {
#           connection(0)    : d0nt_buf0/A;
#         }
#     }
# }

# Segment the boundary scan to be used during logic test
# set_config_value $spec/BoundaryScan/max_segment_length_for_logictest  80


# set_config_value $spec/BoundaryScan/pin_order_file ./chip_top.pinorder                  


report_config_data $spec

# Generate and insert the hardware
process_dft_specification 

# Extract IJAG network and create ICL file for the design
extract_icl -create_ijtag_graybox on

# Create patterns(testbenches) to verify the inserted DFT logic
set spec [create_patterns_specification]
report_config_data $spec

process_pattern_specification

# Point to the libraries and run simultion
set_simulation_library_sources -v ../../library/standard_cells/verilog/*.v \
                               -y ../../library/plls \
                               -y ../../library/memories \
                               -extension v

#run_testbench_simulations
run_testbench_simulations -simulator vcs \
        -compilation_options "-kdb +define+debussy +incdir+/data/project/t2023/ssn_ref/wrapped_cores/processor_core/rtl" \
        -simulator_options "-kdb -debug_access+all"

exit
