http://vmcc.vicp.net:9090/wiki/ 2026-04-19T21:00:13+00:00 http://vmcc.vicp.net:9090/wiki/ http://vmcc.vicp.net:9090/wiki/lib/tpl/dokuwiki/images/favicon.ico text/html 2024-02-02T09:24:39+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=fpga:7series_libraries&rev=1706837079&do=diff 7Series_Libraries CARRY4可以用来做delay chain text/html 2024-02-04T03:49:45+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=fpga:fpga%E8%AE%BE%E8%AE%A1%E8%BF%9B%E9%98%B63&rev=1706989785&do=diff FPGA设计进阶3 ref: <https://blog.csdn.net/Archar_Saber/article/details/123663051> text/html 2023-03-17T10:12:24+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=fpga:gtx%E9%80%9F%E5%BA%A6&rev=1679019144&do=diff 1. gtx速度 2. FMC卡接口标准 <https://fmchub.github.io/appendix/VITA57_FMC_HPC_LPC_SIGNALS_AND_PINOUT.html> * ANSI/VITA 57.1 - Revised2019 FMC: FPGA Mezzanine Cards Base Standard * ANSI/VITA 57.4 - Revised2018 FMC+: FPGA Mezzanine Cards Base Standard - Next Generation text/html 2023-03-17T10:12:24+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=fpga:linux%E8%B0%83%E8%AF%95pcie%E5%91%BD%E4%BB%A4&rev=1679019144&do=diff linux调试pcie命令 setpci lspci text/html 2023-03-17T10:12:24+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=fpga:noc&rev=1679019144&do=diff noc noc: network on chip NoC和互联IP 供应商有Arteris、NetSpeed和Sonics。 NetSpeed 2018年被英特尔收购， Sonics于2019年3月又被Facebook纳入旗下， 至此Arteris成了片上网络(NoC)互联IP市场唯一的IP供应商。 text/html 2023-03-17T10:12:24+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=fpga:pcie_fpga%E5%AE%9E%E7%8E%B0%E6%96%B9%E6%A1%88%E5%8F%82%E8%80%83&rev=1679019144&do=diff FPGA实现方案 1. riffa 支持win7, linux * <https://github.com/KastnerRG/riffa.git> * <https://gitee.com/zyq-77/riffa> 没有专门的register配置接口，应该是需要通过DMA数据的方式实现替代的register配置功能，使用上比较麻烦，没有具体的使用过。 2. xdma * XILINX XDMA pcie 使用 这个IP更好一些，因为它有一个专门的配置register的接口，然后再带了几个专门的DMA接口。功能分开，方便好用。 text/html 2023-03-17T10:12:24+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=fpga:petalinux&rev=1679019144&do=diff petalinux 1. create project source /xilinx/settings.sh petalinux-create -t project --template zynq -n xxx_name petalinux-config --get-hw-description . 2. create modules 相当于创建linux模块驱动 petalinux-create -t modules -n xxx_module --enable text/html 2023-03-17T10:12:24+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=fpga:usb%E6%8E%A5%E5%8F%A3%E8%8A%AF%E7%89%87&rev=1679019144&do=diff USB接口芯片 CYUSB3014 <https://www.infineon.com/cms/en/product/universal-serial-bus-usb-power-delivery-controller/peripheral-controllers/ez-usb-fx3-superspeed-usb-3.0-peripheral-controller/> CY7C68013 <https://www.infineon.com/cms/en/product/universal-serial-bus-usb-power-delivery-controller/peripheral-controllers/ez-usb-fx2lp/> text/html 2023-03-17T10:12:24+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=fpga:vivado%E5%9C%A8%E7%BA%BF%E6%96%87%E6%A1%A3&rev=1679019144&do=diff vivado在线文档 * <https://docs.xilinx.com/home> * <https://docs.xilinx.com/r/en-US/ug893-vivado-ide> text/html 2023-03-17T10:12:24+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=fpga:xilinx_axi_interconnect&rev=1679019144&do=diff AXI interconnect AXI互连 1. axi interconnect v2.1 可支持多slave， 多master 下图是一个整体框图，使用时必须在要IP Integrator模式（block design BD模式）才能使用，即需要事先设计模块打包成IP，然后在那界面再连接。 text/html 2023-03-17T10:12:24+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=fpga:xilinx_fpga%E7%A8%8B%E5%BA%8F%E5%8A%A0%E8%BD%BD%E6%85%A2%E7%9A%84%E5%8E%9F%E5%9B%A0%E5%92%8C%E8%A7%A3%E5%86%B3%E6%8E%AA%E6%96%BD&rev=1679019144&do=diff Xilinx FPGA程序加载慢的原因和解决措施 <https://bbs.elecfans.com/jishu_1949548_1_1.html> 如果是从spi flash启动的话，需要提高SPI的速度，具体做法就是在约束里面增加语句： set_property BITSTREAM.CENERAL.COMPRESS TRUE [current_design] set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]… text/html 2023-03-17T10:12:24+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=fpga:xilinx%E4%BB%BF%E7%9C%9Fdump%E6%B3%A2%E5%BD%A2&rev=1679019144&do=diff xilinx仿真dump波形 点开仿真后，在命令行source dump_vcd.tcl, 即可dump出来预期的波形 open_vcd xsim_dump_vlen0_ch0_tx.vcd log_vcd -level 2 /board/EP/ log_vcd /board/EP/uart_sniffer* log_vcd /board/EP/rx_stream_arbiter/* log_vcd /board/EP/pcie_misc_ctl/* log_vcd /board/EP/tx_stream_demux/* log_vcd /board/EP/PXIE_F4G_100M_top_ch* run 800us #close_vcd text/html 2023-03-17T10:12:24+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=fpga:zynq%E5%AD%A6%E4%B9%A0&rev=1679019144&do=diff zynq 1. 使用axi pkg ip 当使用axi接口的自定义IP时，打包的时候可能要记得在.h文件中添加如下内容 #include "xil_types.h" #include "xstatus.h" #include "xil_io.h" 不然可能在使用define macro访问AXI IP内容的register时，会出现c编译错误。 -- 会不会添加一个axi gpio ip也能解决， 或者手动在程序.h文件里面把 text/html 2023-03-17T10:12:24+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=fpga:%E6%91%84%E5%83%8F%E5%A4%B4&rev=1679019144&do=diff 摄像头 OV5640