wiki edastudy:tessent

edastudy:tessent:atpg

Anonymous (anonymous@undisclosed.example.com) — 2025-03-16T14:29:34+00:00

1. atpg 1.1 Transition AC DC的时候scan_en为0时，只有一拍时钟， scan_en下降沿与这一拍时钟的距离可以足够远，这个时钟也可以是高速或低速时钟。 AC的时候scan_en为0时，有两拍高速时钟（这里也可以配置为低速时钟，shift_as_capture mode）

edastudy:tessent:clock

Anonymous (anonymous@undisclosed.example.com) — 2024-07-18T09:40:51+00:00

clock 1. LE TE A for clock-off, B for leading edge, and C for trailing edge events 2. 同步时钟 add_clocks 0 shift_clock 3. 异步时钟 add_clocks REF_CLK -period 20ns 4. generated时钟 add_clocks PLL_1/pll_clock_0 -reference REF_CLK -freq_multiplier 16 -freq_divider 5

edastudy:tessent:dft_signals

Anonymous (anonymous@undisclosed.example.com) — 2024-10-07T09:03:07+00:00

1. dft signals table_1 table_2 table_3 list the pre-registered static DFT signals. table_4 Table 4 lists the pre-registered dynamic DFT signals. 1.1 Table 1 Pre-Registered Static Global DFT Control Signal Names all_test bscan_clamp_enable

edastudy:tessent:dft_spec

Anonymous (anonymous@undisclosed.example.com) — 2024-11-12T16:56:39+00:00

dft spec 1. create_dft_specification create_dft_specification [-existing_ijtag_host_scan_in host_scan_in_design_pin_spec] [-existing_primary_tap_scan_out primary_tap_client_scan_out_design_pin_spec] [-existing_bscan_host_scan_in bscan_host_scan_in_design_pin_spec] [-tile_ijtag_host_list tile_ijtag_hosts] [-stap_host_list stap_nodes] [-active_high_compliance_enables enable_port_name ...] [-active_l…

edastudy:tessent:drc

Anonymous (anonymous@undisclosed.example.com) — 2024-07-18T09:42:01+00:00

DRC 1. Clock Rules (C Rules) 1.1 C1 When all clocks are at their off state as defined with the add_clocks command, all clock inputs (including sets and resets) of scan and non-scan cells must be at their off state. For non-scan cell violations, the tool converts these to

edastudy:tessent:eco_commands

Anonymous (anonymous@undisclosed.example.com) — 2025-05-22T14:23:54+00:00

eco commands 用于在insertion添加eco逻辑进去。不建议使用process_top_module_connections命令，这个命令是站在顶层，然后穿层次到模块里面的信号的连接，会自动开port，连接，不是一个好的tile flow。

edastudy:tessent:flow

Anonymous (anonymous@undisclosed.example.com) — 2023-11-13T15:32:21+00:00

其它flow执行相关 1. read第三方ip 比如在read_icl第三方ip时，如果是在RTL阶段，先不要把TCD文件弄进来，不要读，也不要放在icl文件对应的目录（工具会自动查找），不然此时它会在check design rules的时候trace scan cell。

edastudy:tessent:icl

Anonymous (anonymous@undisclosed.example.com) — 2025-01-23T10:13:15+00:00

1. icl keep_active_during_scan_test属性，如果icl里例化了其它icl instance, 此属性以最外层的为准。比如icl a 包了icl b 模块，以icl a的属性为准。 * true，模块所有register不上scan chain * false，模块所有register可以上scan chain

edastudy:tessent:ijtag

Anonymous (anonymous@undisclosed.example.com) — 2025-06-17T10:19:13+00:00

ijtag 1. 添加TDR 1.1 JTAG TDR 即直接由TAP IR选择的TDR，不是在ijtag SIB下面的。 IjtagNetwork { HostScanInterface(id) { Tap(id) { HostIjtag(TDR1) { instruction_codes : 4'b0001; instruction_name : TDR1; Tdr(tdr1) { // TDR就是直接在IR指令选 length: 8; extra_bits_capture_value: self; } } HostIjtag(TDR2) { instruction_codes : 4'b0010; instruction_name : TDR2; Tdr(tdr2) { // TDR就是直接在IR指令选 length: 8; …

edastudy:tessent:ist

Anonymous (anonymous@undisclosed.example.com) — 2024-12-25T11:37:38+00:00

IST(in-system test) 是用于车规级等安全性要求比较高的芯片场景。主要是IST可以支持产生JTAG信号，用于在线控制logic bist & memory bist等。其中如果为了加速memory bist, 可以使用BAP的DirectAccess 来控制（这块与IST产生的JTAG接口没有关系）。

edastudy:tessent:lbist

Anonymous (anonymous@undisclosed.example.com) — 2024-07-11T11:16:06+00:00

LBIST 利用logicbist controller逻辑控制EDT channel，经过EDT解压缩产生每条scan chain的输入，产生scan_en，采样每条scan chain的输出，经过MISR积累后进行比较。 1. lbist_setup // ------------------------------------------------------------ // lbist_setup[2:0] lbist_en Mode lbist_run_mode // ------------------------------------------------------------ // 001 X Long Setup 0 // 010 1 Default logicbist Run 1 // 011 1 Normal logicb…

edastudy:tessent:libcomp

Anonymous (anonymous@undisclosed.example.com) — 2024-11-11T10:11:58+00:00

1. libcomp 将.v文件转换成mdt文件 libcomp *.v -dofile

edastudy:tessent:memory_bist

Anonymous (anonymous@undisclosed.example.com) — 2025-07-03T08:13:32+00:00

1. mbist 1.1 memory bist mbist测试由mbist fsm控制， mbist controller/MBISTPG_FSM/STATE表示mbist fsm状态，RUNTEST_EN表示正在跑mbist测试。 mbist结果： MBISTPG_DONE = 1表示mbist测试结束。此时如果MBISTPG_GO为1，表示mbist测试PASS，否则为FAIL。

edastudy:tessent:pattern_spec

Anonymous (anonymous@undisclosed.example.com) — 2024-10-17T14:05:48+00:00

pattern spec 1. 设置pattern tck period PatternsSpecification(design_name, design_id, pattern_id) { IjtagRetargetingOptions { tck_period : 20ns; } Patterns(patterns_name) { } } 2. 设置function clock period 让仿真时，相应时间port/pin有时钟产生。

edastudy:tessent:pdl

Anonymous (anonymous@undisclosed.example.com) — 2024-12-19T16:16:29+00:00

1. PDL iNote "tessent_pragma iReadVar readvar inst1.dataout[7:5] 0b101" iNote "tessent_pragma iWriteVar inst1.writevar[2:3] inst1.datain[1:0]" iNote "tessent_pragma iReadVar readpo dout1,dout2[1:0],dout3 0xA"

edastudy:tessent:simulation

Anonymous (anonymous@undisclosed.example.com) — 2024-07-04T08:36:16+00:00

simulation 指定stdcell,io,memory等模块的仿真模型 set_simulation_library_source -f ./all_model.f 设置VCS安装目录 setenv VCS_HOME /tools/syn/vcs_mx-2022.6-SP1/ 运行仿真命令指定仿真器是vcs run_testbench_simulations \ -parallel_simulations 10 \ -simulator vcs \ -compilation_options {-kdb +define+debussy} \ -simulator_options {-kdb -debug_access+all -debug_region=cell+lib -lca} \ -extra_verilog_files {../rtl/b.v ../rtl/c.v} \ -extra_top_modules module_name_list \ -use_design_view_per_simulation on…

edastudy:tessent:ssn

Anonymous (anonymous@undisclosed.example.com) — 2024-11-26T15:46:46+00:00

ssn 1. ijtag streaming interface 设置streaming interface为ijtag, 即可以通过JTAG接口来输入scan test pattern。此时edt 和 occ slow clock都来自于ssn host, 由tck分频而来。 scan_en=0时，occ切换到fast clock进行正常的at-speed capture操作。

edastudy:tessent:ssn_datapath

Anonymous (anonymous@undisclosed.example.com) — 2024-07-17T10:50:14+00:00

1. datapath 1.1 pipeline 有三种pipeline, 这三种pipe从端口上来看时序是一样的，最终效果都是用正沿打一拍。 Receiver1xPipeline 前一级是用正沿打出来的，这里先用负沿打一下是为了修hold。比如前级reg的clk tree比较短，后级的clk tree比较长，这样后级采样的时候hold容易出问题。

edastudy:tessent:ssn_scandump

Anonymous (anonymous@undisclosed.example.com) — 2025-06-04T14:30:22+00:00

ssn_scandump EDT添加single chain bypass mode # 串scan chain 在single chain两头分别设置一个marker，方便工具取出对应字段, marker得用shift_capture_clock来移数据。\\ edt channel pipeline时钟选shift_capture_clock，避免后面single chain时报T24问题（edt_clock和shift_capture_clock不是同一个时钟）跑ijtag stream接口测试chain test。把对应的jtag操作抄下来，写pattern -ijtag测试case。 # 修改ssn host配置设置enable_shift_reg = 1 设置disable_first_scan_load_masking = 1. 修改total_shift_cnt_minus_one到一个比较大的值，比如为single chain长度+500，大一点没有关系。 # jtag shift single chain iScan ijtag N_cycles…

edastudy:tessent:tcd

Anonymous (anonymous@undisclosed.example.com) — 2023-11-14T10:07:15+00:00

1. tcd example 1.1 rtl tcd Core(gps_baseband) { DesignInfo { design_id : rtl1; design_level : physical_block; ChildBlockModules { } Clocks { Clock(clk) { domain_label : clk; type : async_source; base_period : 3.00ns; period : 3.0; posedge_scannable_flop_count : 7762; negedge_scannable_flop_count : 0; posedge_non_scannable_flop_count : 0; negedge_non_scannable_flop_count : 0; active_high_latc…

edastudy:tessent:tessent_occ

Anonymous (anonymous@undisclosed.example.com) — 2025-08-08T14:12:52+00:00

tessent occ 1. operation mode 1.1 function mode functional mode (test_mode = 0) that enables the fast clock gater to supply a fast clock to the design. 1.2 shift mode shift mode (scan_en = 1) that uses the slow_clock to load and unload the scan chains, including the condition bits in ShiftReg.

edastudy:tessent:tessent_user_arg

Anonymous (anonymous@undisclosed.example.com) — 2024-01-09T16:20:43+00:00

tessent_user_arg #!/bin/sh #\ exec tessent -shell -dofile "$0" -arguments ${1+"$@"} set_transcript_style off puts "$tessent_user_arg" # add dofile commands here array set ar $tessent_user_arg puts "$ar(a)" puts "$ar(b)" puts "$ar(c)" exit 命令： ./xxxx a=5 b=6 c=7

edastudy:tessent:test_setup

Anonymous (anonymous@undisclosed.example.com) — 2025-06-05T08:05:58+00:00

test_setup source xxx.pdl set_test_setup_icall xxx_proc -end; # 可以在工具推出来的setup后面加上自己的pdl设置。

edastudy:tessent:tile_flow

Anonymous (anonymous@undisclosed.example.com) — 2023-08-23T21:23:39+00:00

tile flow 1. 第一步：修改RTL源文件, tile创建port, 在顶层把这些port连起来注：不需要使用在顶层使用create_connection去连接，这个命令有使用限制。 process_top_module_connections Context: dft Mode: setup, analysis

edastudy:tessent:常见问题

Anonymous (anonymous@undisclosed.example.com) — 2023-12-12T20:07:24+00:00

常见问题 * 电源被关闭，导致无法继续测试， -- 尝试在测试时把电源相关的控制钳住。