http://vmcc.vicp.net:9090/wiki/ 2026-04-21T17:17:57+00:00 http://vmcc.vicp.net:9090/wiki/ http://vmcc.vicp.net:9090/wiki/lib/tpl/dokuwiki/images/favicon.ico text/html 2024-03-12T09:50:45+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=edastudy:dc:dc_cmd&rev=1710208245&do=diff dc cmd 1. link_library target_library set link_library "* lib1.db lib2.db" set link_library {* lib1.db lib2.db} set target_library $link_library #注意.db是一定要加的，是db完整的名字，不能省略 2. editing designs 3. set_input_delay text/html 2023-04-24T08:40:18+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=edastudy:dc:multicycle&rev=1682296818&do=diff multicycle 1. default is single cycle timing 2. multicycle setup timing 3. multicycle hold timing 默认的hold timing check点是在capture cycle的前一个cycle, 基本要求是path delay必须要达到5个cycle,即10ns, 这显然是不合理的。 text/html 2026-03-17T18:59:33+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=edastudy:dc:%E5%85%B6%E5%AE%83&rev=1773745173&do=diff 标题 1. dc report_timing 为了把clock path都报全，不能把clock network当着是ideal。 set_propagated_clock $clk_obj ;# 让DC传播时钟延迟（关键！） 然后再报，就不是ideal clock了。 text/html 2023-03-17T10:12:24+00:00 Anonymous (anonymous@undisclosed.example.com) http://vmcc.vicp.net:9090/wiki/doku.php?id=edastudy:dc:%E6%A3%80%E6%9F%A5%E9%A1%B9&rev=1679019144&do=diff 检查项 * 检查register cell是不是既带复位又带置位，如果是的话，这两端是否需要时序检查。 *