ETAssemble Tool Reference.Pad Library.Function

Attribute Descriptions

Tessent LV Flow Pad Library Mappings

model model_name (list_of_pins) (
  model_source = verilog_module; 
  cell_type = { clock_gating_and | clock_gating_or | 
    buffer | inverter | or | and | nand | nor |     xor | mux |  
    clock_buffer | clock_inverter | clock_and | clock_or | clock_mux |
    clock_dff | clock_shaper | dff | latch | synchronizer_cell |
    scan_cell | pad | prohibited };  
  simulation_function = { clock_gating_and | clock_gating_or | 
    func_only_clock_gating_and | func_only_clock_gating_or |
    clock_shaper_reset_active | clock_shaper_reset_inactive | buffer |
    inverter | or | and | nand | nor | xor | mux | dff | latch |
     synchronizer_cell | scan_cell | tie0 | tie1 } ; 
  pad_ac;
  pad_nonjtag; 
  pad_ac_lp_time = <time_in_seconds>; 
  pad_ac_hp_time = <time_in_seconds>; 
  pad_ac_hp_on_chip;
  bcell_lib_name = <bcell_lib_name>
  nonscan_model = model_name | model_name (list_of_pins);
  nonscan_equivalents = model_name1, modelname2 ...; 
  scan_equivalents = model_name1, modelname2 ...; 
  scan_length = integer;
  gated_out_scan_cell;
  mode(
    pad_ac;
    pad_ac_lp_time = <time_in_seconds>; 
    pad_ac_hp_time = <time_in_seconds>; 
    pad_ac_hp_on_chip [Yes | No]; 
    input (pin_name) (
      [pad_to_pad] [pad_pad_io][pad_pad_io_inv] [pad_enable_high]
      [pad_enable_low] [pad_to_sje_mux_low] [pad_to_sje_mux_high] 
      [pad_to_sji_mux] [pad_to_sjo_mux] [pad_select_jtag_enable] 
      [pad_select_jtag_in] [pad_select_jtag_out] 
      [pad_two_state_output_enable_high]
      [pad_two_state_output_enable_low]
      [pad_init_data_dot6] [pad_init_data_inv_dot6] 
      [pad_init_posedge_clock_dot6] [pad_init_negedge_clock_dot6] 
      [pad_init_enable_high_dot6] [pad_init_enable_low_dot6] 
      [pad_ac_mode_dot6] 
      [pad_data_inv]       [pad_diff_voltage] [pad_diff_current]    
      [pad_from_io] [pad_from_io_inv] [pad_tied0] [pad_tied1] 
      [pad_open]) 
    ) // end input section of mode 
 
    input (pin_name2) () 
    ... 
    input (pin_nameN) () 
 
    output(pin_name) (
      [pad_from_pad] [pad_pad_io] [pad_pad_io_inv] 
      [pad_from_sje_mux] [pad_from_sji_mux] [pad_from_sjo_mux] 
      [pad_sample_pad]       [pad_data_inv] [pad_diff_voltage]
      [pad_diff_current] pad_open_drain] [pad_open_source] 
      [pad_to_io] [pad_to_io_inv] [pad_pull0] [pad_pull1]; 
    ) // end output section of mode 
    output (pin_name2) () 
    ... 
    output (pin_nameN) () 
 
    inout(pin_name) (
      [pad_pad_io] [pad_pad_io_inv][pad_diff_voltage]
      [pad_diff_current] [pad_open_drain] 
      [pad_open_source][pad_pull0] [pad_pull1]
    ) // end inoutsection of mode 
 
    inout (pin_name2) () 
    ... 
    inout (pin_nameN) () 
 
  )// end mode 
 
// Completed model level statements, including pad modes if any.
// Define model interface port directions, and attributes. 

  intern (intern_nodes) (intern_attributes)
  input (pin_names) (list_of_input_attributes)
  output (pin_names) (list_of_output_attributes)
  inout (pin_names) (list_of_inout_attributes)
 
// Define hardware simulation function using cell library
// primitives and instances 
  ( 
    //hardware_statements, see Hardware Definitions 
  ) 

) // end model_name 

model ipad
(PAD, C)
(         
model_source = verilog_module;
cell_type = pad;              

input (PAD) ( pad_from_io; )
output (C) ( pad_from_pad; )
(                           
instance = buf02 ipad_inst (PAD, C);
)                                     
) // end model ipad 

带EN控制

model ipad_ien
(PAD, C, IEN)
(         
model_source = verilog_module;
cell_type = pad;              

input (PAD) ( pad_from_io; )
input (IEN) ( pad_input_enable_high; )
output (C)  ( pad_from_pad; )
(     
// Input a 0 (low voltage) to core when input disabled.
primitive = _and mlc_and (PAD, IEN, C);
)                                     
) // end model ipad_ien

差分PAD

model Diff_Pad
  (C,PADP,PADN)
(
  cell_type = pad;

  input (PADP) ( pad_from_io; pad_diff_voltage)
  input (PADN) ( pad_from_io_inv; )
  output (C) ( pad_from_pad )

  (

primitive = _buf P1 (PADP, diff_net);
primitive = _inv P2 (PADN, diff_net);
primitive = _buf P3 (diff_net, C);

   )
)

属性pad_open_drain与pad_open_source生成出来的rtl电路区别:
仅在输出Z态的控制逻辑不一样：

• OD输出Z态时需要把数据输入force为1
• OS输出Z态时需要把数据输入force为0

在数据输入pin上加入pad_data_inv与不加的区别：
OD情况：

OS情况：

只能驱动输出0， 数据输入1时，输出0， 数据输入0时高阻

model od_pad
 (DO, PAD)
(
   model_source = verilog_module;
   cell_type = pad;
   mode(
     pin (DO) ( pad_to_pad; pad_data_inv;)
     pin (PAD) (pad_pad_io; pad_pull1; pad_open_source;)
   )
   input (DO) ( )
   inout (PAD) ( )
   (
     primitive = _pull mlc_pull_1 (1, PAD);

     primitive = _tsh mlc_tsh_1 (0, DO, PAD);
   )
)

verilog mode

module od_pad (DO, PAD);
input   DO;
inout   PAD;
 
pullup(PAD);
 
assign PAD = (DO == 1'b1) ? 1'b0 : 1'bz;
 
endmodule

只能驱动输出0， 数据输入0时，输出0， 数据输入1时高阻

model od_pad
 (DI, DO, PAD)
(
   model_source = verilog_module;
   cell_type = pad;

  mode(
    pin (PAD) (pad_pad_io; pad_pull1; pad_open_drain;)
    pin (DO) (pad_to_pad; )
    pin (DI) (pad_from_pad; )
  )

   input (DO) ( )
   inout (PAD) ( )
   output (DI) ( )
   (
     primitive = _buf mlc_buf_1 (PAD, DI);
     primitive = _pull mlc_pull_1 (1, PAD);

     primitive = _inv   mlc_inv_1  (D0, DOinv);
     primitive = _tsh mlc_tsh_1 (D0, DOinv, PAD);
   )
)

module od_pad (DI, DO, PAD);
output  DI;
input   DO;
inout   PAD;
 
pullup(PAD);
 
assign PAD = (DO == 1'b0) ? 1'b0 : 1'bz;
assign DI = PAD;
 
endmodule

只能驱动输出0， 数据输入1时，输出0， 数据输入0时高阻

model od_pad_inv
 (DI, DO, PAD)
(
   model_source = verilog_module;
   cell_type = pad;

  mode(
    pin (PAD) (pad_pad_io; pad_pull1; pad_open_source;)
    pin (DO) (pad_to_pad; pad_data_inv;)
    pin (DI) (pad_from_pad; )
  )

   input (DO) ( )
   inout (PAD) ( )
   output (DI) ( )
   (
     primitive = _buf mlc_buf_1 (PAD, DI);
     primitive = _pull mlc_pull_1 (1, PAD);

     primitive = _inv   mlc_inv_1  (DO, DOinv);
     primitive = _tsh mlc_tsh_1 (DOinv, DO, PAD);
   )
)

module od_pad_inv (DI, DO, PAD);
output  DI;
input   DO;
inout   PAD;
 
pullup(PAD);
 
assign PAD = (DO == 1'b1) ? 1'b0 : 1'bz;
assign DI = PAD;
endmodule

只能驱动输出0， 数据输入1时，输出0， 数据输入0时高阻
这种仿真会出错，因为pad_open_drain输出Z时会把DO force为1，但电路输出为0，比较不过。
这时候可以把生成出来的电路换成OS生成出来的电路，仿真可以PASS

model od_pad_inv
 (DI, DO, PAD)
(
   model_source = verilog_module;
   cell_type = pad;
  mode(
    pin (PAD) (pad_pad_io; pad_open_drain;)
    pin (DO) (pad_to_pad; pad_data_inv;)
    pin (DI) (pad_from_pad; )
  )
   input (DO) ( )
   inout (PAD) ( )
   output (DI) ( )
   (
     primitive = _buf mlc_buf_1 (PAD, DI);

     primitive = _inv   mlc_inv_1  (DO, DOinv);
     primitive = _tsh mlc_tsh_1 (DOinv, DO, PAD);
   )
)

module od_pad_inv (DI, DO, PAD);
output  DI;
input   DO;
inout   PAD;
 
assign PAD = (DO == 1'b1) ? 1'b0 : 1'bz;
assign DI = PAD;
endmodule