A for clock-off, B for leading edge, and C for trailing edge events
add_clocks 0 shift_clock
add_clocks REF_CLK -period 20ns
add_clocks PLL_1/pll_clock_0 -reference REF_CLK -freq_multiplier 16 -freq_divider 5
要注意async clock 与 sync clock的区别,定义不同。