VCS_MX為mixed hdl仿真器，支持vhdl+verilog+sv的混合仿真。 VCS則是verilog+sv的 VC LP // Low Power Signoff and Static Verification (rtl & post) VC Forma l // Next-Generation Formal Verification VC Formal DPV (Datapath Validation) // VC Formal Datapath Validation (DPV) App with integrated HECTOR™