====== vcs使用 ======

===== - ucli =====

simv [simv_options] -ucli

<code>
% simv -ucli
ucli%
# 输入help可以查看命令
</code>

交互脚本方式: simv -ucli -i ucli_script.inc

交互脚本是tcl格式的，可以使用for循环。

<code tcl>
for {set i 0} {$i < 8} {incr i} {
    force a 1
    run 10ns
    force top.b 0
    run 10ns
    force b\[0\] 1; # force b[0]为1， 需要加\
}
</code>


force 命令注意，只能force信号为具体的值，不能force一个信号到另外一个信号\\
force到的具体值需要给完整的宽度，比如8'd28,  不能直接给28,可能会有宽度不匹配的问题，导致force失败。\\
force 信号最好给完整的信号hier名，尤其是有的仿真设置了多个-top



===== - 给register赋初始值 =====
这是为了在netlist仿真的时候，有一些不带reset/set的register给其赋个初始值，避免X态传播。
<code>
+vcs+initreg+random option must be specified at compile time

# 以下可以在run simv时指定
+vcs+initreg+0
+vcs+initreg+1
+vcs+initreg+random      // 采用赋随机值
+vcs+initreg+seed_value
</code>


===== - 后仿时timing violation避免产生X态 =====

在编译时加上 ''+no_notifier'' 选项。

===== - plusargs =====

<code verilog>
initial begin
  if($test$plusargs("test")) begin
    $display("haha");
  end
end
</code>

<code>
./simv+test
</code>

===== - 反标率 =====
<code>
% vcs -diag=sdf:verbose example.v
% simv
% cat sdfAnnotateInfo
The following is the output:
Static entries in elaborated design under "test":
         Annotated by SDF "example.sdf":
         No. of Pathdelays   = 4  Annotated = 50.00%
         No. of Tchecks      = 4  Annotated = 50.00%
                                            Total            Annotated  Percentage
         IOPATH                                 4                    2       50.00%
         Path Delays Summary of above
         SETUPHOLD                              4                    2       50.00%
         Timing checks Summary of above

 OverAll Static entries in elaborated design:
         No. of Pathdelays   = 4  Annotated = 50.00%
      No. of Tchecks      = 4  Annotated = 50.00%
                                            Total            Annotated  Percentage
         IOPATH                                 4                    2       50.00%
         Path Delays Summary of above
</code>

===== - kdb =====

<code bash>
# VCS Two-step Flow Compilation:
% vcs -debug_access+r -sverilog -kdb top.v

# VCS Three-step Flow Compilation:
% vlogan top.v -kdb
% vcs top -debug_access+r -kdb
</code>

===== - rand seed =====

<code verilog>

reg     [31:0]  seed;
reg     [31:0]  ret;
initial begin
    if ($value$plusargs("seed=%d",seed)) begin
        $display("seed = %0d", seed);
        ret = $urandom(seed);

        repeat(2) begin
            ret = $urandom();
            $display("ret = %0x", ret);
        end
        $finish;
    end
end
</code>

<code bash>
./simv +seed=21
seed = 21
ret = c7466bae
ret = cf3f2455


./simv +seed=22
seed = 22
ret = 4c85682
ret = 2c3fd11a


</code>


<code perl>
# perl gen seed
srand;
$rand_seed = int (rand(100000));
</code>