====== - datapath ======

===== - pipeline =====

有三种pipeline, 这三种pipe从端口上来看时序是一样的，<color #ed1c24>最终效果都是用正沿打一拍</color>。

**Receiver1xPipeline**

前一级是用正沿打出来的，这里先用负沿打一下是为了修hold。
比如前级reg的clk tree比较短，后级的clk tree比较长，这样后级采样的时候hold容易出问题。

{{:edastudy:tessent:pasted:20240528-202232.png?nolink}}

**Pipeline**

{{:edastudy:tessent:pasted:20240528-202246.png?nolink}}

**OutputPipeline**

{{:edastudy:tessent:pasted:20240528-202258.png?nolink}}



**RxPipeline**

{{:edastudy:tessent:pasted:20240528-204754.png?nolink}}



===== - example =====

<code>
    DataPath(1) {
      output_bus_width       : 2;
      ScanHost(1) {
      }
      Pipeline(4) {
      }
      Multiplexer(1) {
          Connections {
              secondary_bus_data_in  : s0_busin[1:0];
          }
          Pipeline(33) {
          }
          Receiver1xPipeline (rx22) {
          }
      }
      Pipeline(2) {
      }
      Pipeline(1) {
        ExtraOutputPath {
            Connections {
              // bus_clock_out      : s0_bus_clock_out;
              bus_data_out       : s0_busout[1:0];
            }
            Pipeline(11) {
            }
        }
      }
      Receiver1xPipeline (rx0) {
      }
    }
</code>


<flow>
graph LR
ssn_busin-->rxpipe0
rxpipe0-->pipe1
pipe1-->pipe2
pipe2-->mux1
pipe1-->pipe11;
pipe11-->s0_busout;
s0_busout -.->s0_busin
s0_busin-->rxpipe22
rxpipe22-->pipe33
pipe33-->mux1



mux1-->pipe4
pipe4-->ssh
ssh-->ssn_busout
</flow>