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edastudy:tessent:dft_signals
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===== - dft signals ===== [[edastudy:tessent:dft_signals#table_1]] [[edastudy:tessent:dft_signals#table_2]] [[edastudy:tessent:dft_signals#table_3]] list the pre-registered static DFT signals. [[edastudy:tessent:dft_signals#table_4]] Table 4 lists the pre-registered dynamic DFT signals. ==== - Table 1 ==== ^ Pre-Registered Static Global DFT Control Signal Names ^ | all_test | | bscan_clamp_enable | | bscan_input_isolation_enable | | output_pad_disable | | dft_signal_disable | | occ_kill_clock_en | | ssn_en | | tck_occ_en | | tck_select | | tristate_enable_nc_test | | tristate_enable_nc_test_type | ==== - Table 2 ==== ^ Pre-Registered Static Logic Test Control Signal Names ^ | async_set_reset_static _disable | | capture_per_cycle_static_en | | control_test_point_en | | ext_ltest_en | | ext_lbist_en | | int_ltest_en | | lbist_en | | lbist_low_power_shift_en | | lbist_self_test_en | | ltest_en | | mcp_bounding_en | | memory_bypass_en | | observe_test_point_en | | se_pipeline_en | | wrapper_toggle_en | | x_bounding_en | ==== - Table 3 ==== ^ Pre-Registered Static Scan Mode Signal Names ^ | controller_chain_mode | | edt_mode | | ext_edt_mode | | ext_mode | | ext_multi_mode | | ext_single_mode | | int_edt_mode | | int_mode | | int_multi_mode | | int_single_mode | | multi_mode | | promoted_cells_mode | | retargeting#_mode = 1, 2, ...,8 | | single_mode | ==== - Table 4 ==== ^ Pre-Registered Dynamic DFT Signal Names ^ | async_set_reset_dynamic_disable | | capture_per_cycle_dynamic_en | | edt_clock | | edt_update | | input_wrapper_scan_en | | lbist_async_set_reset_dynamic_enable | | lbist_misr_accumulate_en | | lbist_prpg_en | | lbist_reset | | output_wrapper_scan_en | | scan_en | | shift_capture_clock | | shift_clock | | capture_clock | | test_clock | === - async_set_reset_dynamic_disable === {{:edastudy:tessent:pasted:20231121-094838.png?nolink}} === - edt_clock === {{:edastudy:tessent:pasted:20231113-111747.png?nolink}} === - shift_capture_clock === {{:edastudy:tessent:pasted:20231113-111826.png?nolink}} === - shift_clock === {{:edastudy:tessent:pasted:20231113-111845.png?nolink}} === - capture_clock === {{:edastudy:tessent:pasted:20231113-111905.png?nolink}} ===== - wavefroms ===== {{:edastudy:tessent:pasted:20231113-111950.png?nolink}} {{:edastudy:tessent:pasted:20231113-112000.png?nolink}} ===== - add_dft_control_points ===== <code tcl> add_dft_control_points pin_port_net_spec [-type type] [-inverse_dft_signal_source] [-dft_signal_source_name dft_signal_source_name [‑parent_instance_of_dynamic_dft_signal parent_instance]] [-ignore_existing_sources] [‑auto_uniquify] [-allow_editing_below_ijtag_instances] </code> add_dft_control_points pllmux/s -dft_signal_source_name pll_bypass {{:edastudy:tessent:pasted:20241007-090122.png?nolink}} {{:edastudy:tessent:pasted:20241007-090132.png?nolink}} {{:edastudy:tessent:pasted:20241007-090139.png?nolink}} {{:edastudy:tessent:pasted:20241007-090145.png?nolink}} {{:edastudy:tessent:pasted:20241007-090207.png?nolink}} {{:edastudy:tessent:pasted:20241007-090213.png?nolink}} ===== - test point insertion ===== <code tcl> Context: dft -test_points Mode: setup, analysis Specifies user-defined control points during test point insertion. Usage add_control_points -location pin/port_spec -type {AND | OR} [-clock clock_pin/port] [-enable enable_pin/port] </code> <code tcl> Context: dft -test_points Mode: setup, analysis Specifies user-defined observe points during test point insertion. Usage add_observe_points -location pin/port_spec [-clock pin/port_spec] [-enable pin/port_spec] </code> ===== - add_dft_clock_mux ===== 在pre-DC阶段之前添加CLOCK MUX,为了是时钟可控,测试时钟可选等等。 <code tcl> add_dft_clock_mux pin_port_net_spec -test_clock_source test_clock_source_spec [‑dft_signal_source_name dft_signal_source_name] [-inverse_dft_signal_source] [-auto_uniquify] </code> <code tcl> add_clocks clka -period 6.7ns > add_clocks vco_buf/Y ‑branch > add_clocks clkb_buf/y ‑branch > register_static_dft_signal_names alt_ref pll_bypass > add_dft_clock_mux clkb -test_clock_source mem1/clk \ -dft_signal_source_name all_test > add_dft_clock_mux pll1/vco -test_clock_source pll1/ref \ -dft_signal_source_name pll_bypass > add_dft_clock_mux pll1/ref -test_clock_source clkb \ -dft_signal_source_name alt_ref > report_dft_clock_mux // Dft clock muxes// =============== // ---------- ----------------- ------------------- // Node Test clock source Control source name // ---------- ----------------- ------------------- // 'clkb' mem1/clk all_test // 'pll1/vco' pll1/ref pll_bypass // 'pll1/ref' clkb alt_ref </code> {{:edastudy:tessent:pasted:20240904-081124.png?nolink}}
edastudy/tessent/dft_signals.txt
· 最后更改: 2024/10/07 09:03 由
user01
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