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====== jtag调试器 ======

主要是关注如何支持多个JTAG DEVICE(chaining multiple targets)

===== - 公共需求 =====

In order to chain targets, the devices must support the following:
  * BYPASS register.
  * The IDCODE instruction must immediately follow a reset of the Test Access Port (TAP).
  * Bit 0 of ID Code must be 1.
  * In CAPTURE-IR state, the fixed value 1 must be loaded into the IR.


===== - Ulink2 =====
没有明确说支持jtag chain device数量, 只能配合Keil使用

https://developer.arm.com/documentation/101455/0100/Using-ULINK2/Chaining-Multiple-Targets


 The results of this scan are displayed in the JTAG Device Chain section of the ARM Target Driver Setup dialog (Project — Options for Target — Debug — Settings).

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===== - Ulink Pro =====
https://developer.arm.com/documentation/101416/0100/Using-ULINKpro/Chaining-Multiple-Targets?lang=en

没有明确说支持jtag chain device数量, 只能配合Keil使用

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===== - Ulink Plus =====
没有明确说可以支持jtag chain, 只能配合Keil使用

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===== - TRACE32 =====
{{edastudy:app_jtag_interface.pdf}}  第23页

在单片系统中，TRACE32可以使用SYStem.DETECT DAP访问DAP中的单根ROM表，对系统进行认证和发现。那么在多芯片系统中是如何实现的呢？

例如，在一个由两个芯片组成的系统中，每个芯片都有自己的DAP和ROM表，这两个DAP连接在雏菊链中。SYStem.DETECT DAP会怎么做？系统是如何识别的？

通过使用SYStem.CONFIG.DAIRPRE、SYStem.CONFIG.DAIRPOST、SYStem.CONFIG.DADRPRE和SYStem.CONFIG.DADRPOST四个命令设置正确的预位和后置位，在JTAG雏菊链中选择DAP。

要为预位和后置位找到正确的值，可以使用命令SYStem.DETECT.SHOWChain。它打开一个窗口，允许您通过上下文菜单直接从那里设置预/后位：

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然后，SYStem.DETECT.DAP检查DAP，它可以使用先前定义的预/后位进行访问。

===== - JLINK =====
https://kb.segger.com/UM08001_J-Link_/_J-Trace_User_Guide#Determining_values_for_scan_chain_configuration

https://www.segger.com/products/debug-probes/j-link/?mtm_campaign=kb&mtm_kwd=jlink

J-Link / J-Trace can handle multiple devices in the scan chain. This applies to hardware where multiple chips are connected to the same JTAG connector. As can be seen in the following figure, the TCK and TMS lines of all JTAG device are connected, while the TDI and TDO lines form a bus.

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^ Specification               ^ Max supported value  ^
| Number of devices in chain  | 32                   |
| Total IR length             | 255                  |

One or more of these devices can be CPU cores; the other devices can be of any other type but need to comply with the JTAG standard.

Sample configurations

^ Device 0 Chip(IR len)  ^ Device 1 Chip(IR len)  ^ Device 2 Chip(IR len)  ^ Position  ^ IR len  ^
| **ARM(4)**             | -                      | -                      | 0         | 0       |
| **ARM(4)**             | Xilinx(8)              | -                      | 0         | 0       |
| Xilinx(8)              | **ARM(4)**             | -                      | 1         | 8       |
| Xilinx(8)              | Xilinx(8)              | **ARM(4)**             | 2         | 16      |
| **ARM(4)**             | Xilinx(8)              | ARM(4)                 | 0         | 0       |
| ARM(4)                 | Xilinx(8)              | **ARM(4)**             | 2         | 12      |
| Xilinx(8)              | **ARM(4)**             | Xilinx(8)              | 1         | 8       |

<code>
//
// JTAG chain:  TDI -> TAP#3 -> TAP#2 -> TAP#1 -> TAP#0
// TAP#3 (ARM DAP): IRLen = 4-bit
// TAP#2 (RISC-V):  IRLen = 5-bit
// TAP#1 (RISC-V):  IRLen = 5-bit
// TAP#0 (custom):  IRLen = 7-bit
//
Connect to TAP#1 (RISC-V):
JTAGConf 7 1  // IRPre = 7, DRPre = 1

Connect to TAP#2 (RISC-V):
JTAGConf 12 2  // IRPre = 7 + 5, DRPre = 1 + 1
</code>

**KEIL JLINK Chain Devices**

https://developer.arm.com/documentation/101453/0100/Use-J-Link-J-Trace/Chain-Devices

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<code>
Connect the control signals in parallel (TMS and TCLK) .
Connect the data signals in series to form a bus (TDO to TDI).
A maximum of 8 chained devices are supported.
</code>

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