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linux:perl:用perl产生verilog文件
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| 两侧同时换到之前的修订记录前一修订版后一修订版 | 前一修订版 | ||
| linux:perl:用perl产生verilog文件 [2023/10/27 22:06] – zhangguo | linux:perl:用perl产生verilog文件 [2023/10/27 22:27] (当前版本) – [1. vpl.pl] zhangguo | ||
|---|---|---|---|
| 行 12: | 行 12: | ||
| <file perl vpl.pl> | <file perl vpl.pl> | ||
| # | # | ||
| - | |||
| if (scalar @ARGV < 1) { | if (scalar @ARGV < 1) { | ||
| - | print " | + | print " |
| exit; | exit; | ||
| } | } | ||
| $ivpl = shift @ARGV; | $ivpl = shift @ARGV; | ||
| - | $opl = $ivpl; | + | $opl = "$ivpl.pl"; |
| - | $opl =~ s/\.\w+$/.opl/; | + | |
| if (scalar @ARGV > 0) { | if (scalar @ARGV > 0) { | ||
| $vfile = shift @ARGV; | $vfile = shift @ARGV; | ||
| } | } | ||
| else { | else { | ||
| - | $vfile = $ivpl; | + | $vfile = "$ivpl.v"; |
| - | $vfile =~ s/\.\w+$/.v/; | + | |
| } | } | ||
| 行 56: | 行 53: | ||
| if ($ret == 0) { | if ($ret == 0) { | ||
| print " | print " | ||
| - | @ar = glob "$opl*"; | + | @ar = glob " |
| - | #print "will delete @ar\n"; | + | |
| foreach $tmp (@ar) { | foreach $tmp (@ar) { | ||
| unlink ($tmp); | unlink ($tmp); | ||
| 行 64: | 行 60: | ||
| exit 0; | exit 0; | ||
| + | |||
| </ | </ | ||
| + | |||
| + | |||
| + | |||
| + | ===== - example ===== | ||
| + | |||
| + | <code bash> | ||
| + | localhost / | ||
| + | generate a.x.v ok! | ||
| + | </ | ||
| + | |||
| + | file: a.x | ||
| + | <code verilog> | ||
| + | module a( | ||
| + | input clk, | ||
| + | |||
| + | ; for ($i=0; $i<10; $i++) { | ||
| + | input data_$i, | ||
| + | ;} | ||
| + | |||
| + | output data_o | ||
| + | ); | ||
| + | |||
| + | ; for ($i=0; $i<10; $i++) { | ||
| + | ; $j = 10 - $i; | ||
| + | // 10 - $j = $i; | ||
| + | ; } | ||
| + | |||
| + | |||
| + | endmodule | ||
| + | </ | ||
| + | |||
| + | output a.x.v: | ||
| + | <code verilog> | ||
| + | module a( | ||
| + | input clk, | ||
| + | |||
| + | input data_0, | ||
| + | input data_1, | ||
| + | input data_2, | ||
| + | input data_3, | ||
| + | input data_4, | ||
| + | input data_5, | ||
| + | input data_6, | ||
| + | input data_7, | ||
| + | input data_8, | ||
| + | input data_9, | ||
| + | |||
| + | output data_o | ||
| + | ); | ||
| + | |||
| + | // 10 - 10 = 0; | ||
| + | // 10 - 9 = 1; | ||
| + | // 10 - 8 = 2; | ||
| + | // 10 - 7 = 3; | ||
| + | // 10 - 6 = 4; | ||
| + | // 10 - 5 = 5; | ||
| + | // 10 - 4 = 6; | ||
| + | // 10 - 3 = 7; | ||
| + | // 10 - 2 = 8; | ||
| + | // 10 - 1 = 9; | ||
| + | |||
| + | |||
| + | endmodule | ||
| + | </ | ||
| + | |||
linux/perl/用perl产生verilog文件.1698415565.txt.gz · 最后更改: 2023/10/27 22:06 由 zhangguo