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edastudy:verilog
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| 两侧同时换到之前的修订记录前一修订版后一修订版 | 前一修订版 | ||
| edastudy:verilog [2025/01/15 15:41] – [7. fwrite] user01 | edastudy:verilog [2025/06/03 16:27] (当前版本) – [9. generate] user01 | ||
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| 行 1: | 行 1: | ||
| ====== verilog ====== | ====== verilog ====== | ||
| + | |||
| + | vcs仿真参考 [[edastudy: | ||
| ===== - 异步复位 ===== | ===== - 异步复位 ===== | ||
| 行 122: | 行 124: | ||
| 如果port width是参数 | 如果port width是参数 | ||
| <code verilog> | <code verilog> | ||
| - | module a #(parameter WIDTH=8)( | + | module a #(parameter WIDTH=8) ( |
| input [WIDTH-1:0] datai, | input [WIDTH-1:0] datai, | ||
| output [WIDTH-1:0] datao | output [WIDTH-1:0] datao | ||
| 行 129: | 行 131: | ||
| endmodule | endmodule | ||
| </ | </ | ||
| + | |||
| + | ===== - generate ===== | ||
| + | <code verilog> | ||
| + | wire [7:0] d; | ||
| + | wire [7:0] q; | ||
| + | wire [7:0] q2; | ||
| + | |||
| + | a u_a[7:0] ( | ||
| + | .clk (clk), | ||
| + | .rst_n | ||
| + | .d (d[7:0]), | ||
| + | .q (q[7:0]) | ||
| + | ); | ||
| + | |||
| + | genvar i; | ||
| + | generate | ||
| + | for (i=0; | ||
| + | a u_a2 ( | ||
| + | .clk (clk), | ||
| + | .rst_n | ||
| + | .d (d[i]), | ||
| + | .q (q2[i]) | ||
| + | ); | ||
| + | end | ||
| + | endgenerate | ||
| + | |||
| + | |||
| + | </ | ||
| + | |||
| + | ===== - 加延时 ===== | ||
| + | |||
| + | <code verilog> | ||
| + | |||
| + | initial begin | ||
| + | forever #5 clk = ~clk; | ||
| + | end | ||
| + | |||
| + | initial begin | ||
| + | #5 rst_n = 1'b1; | ||
| + | end | ||
| + | |||
| + | assign #1 clk2 = clk1; | ||
| + | |||
| + | always @(posedge clk) | ||
| + | data2 <= #1 data1; | ||
| + | |||
| + | </ | ||
| + | |||
| + | ===== - 仿真force注意 ===== | ||
| + | |||
| + | force某一个net时，要意识到，其它这个force会前后传递的\\ | ||
| + | 不只是当前看到的PIN的值被force成期望值, | ||
| + | |||
| + | 如果不想影响更多的点，可能是要想办法把线给断开，只有期望点才会被force。 | ||
edastudy/verilog.1736926875.txt.gz · 最后更改: 2025/01/15 15:41 由 user01