edastudy:vc_formal:user_check

差别

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到此差别页面的链接

--- edastudy:vc_formal:user_check [2026/06/07 14:13] – 创建 user01
+++ edastudy:vc_formal:user_check [2026/06/07 14:19] (当前版本) – user01
@@ 行 1: / 行 1: @@
-#### - user check ####
+==== - user check ====
+=== - vc_check.tcl ===
 <code>
 set search_path "."
@@ 行 15: / 行 16: @@
 }
+</code>
+=== - output ===
+<code>
+cell_name: core_0, ref_name: core, orig_ref_name: core
+cell_name: core_1, ref_name: core, orig_ref_name: core
+cell_name: core_2, ref_name: core_0000, orig_ref_name: core
+cell_name: core_3, ref_name: core_0001, orig_ref_name: core
+cell_name: out, ref_name: SEQ_FF, orig_ref_name: SEQ_FF
+cell_name: I_OR_N_1, ref_name: BITWISE_OR, orig_ref_name: BITWISE_OR
+</code>
+=== - file ===
+chip.v
+<code>
+module chip(
+    in, sel, clk, out
+);
+input   in, clk, sel;
+output  out;
+reg     out;
+core core_0 (
+    .in     (in),
+    .clk    (clk),
+    .sel    (sel),
+    .out    (out_0)
+);
+core core_1 (
+    .in     (out_0),
+    .clk    (clk),
+    .sel    (sel),
+    .out    (out_1)
+);
+core core_2 (
+    .in     (in),
+    .clk    (clk),
+    .rst_n  (1'b0),
+    .sel    (sel),
+    .out    (out_2)
+);
+core core_3 (
+    .in     (in),
+    .clk    (clk),
+    .rst2_n (1'b0),
+    .sel    (sel),
+    .out    (out_2)
+);
+always @(posedge clk) begin
+    out <= out_0 | out_1 | out_2;
+end
+endmodule
 </code>

edastudy/vc_formal/user_check.1780812803.txt.gz · 最后更改: 2026/06/07 14:13 由 user01