edastudy:tessent:drc
差别
这里会显示出您选择的修订版和当前版本之间的差别。
| 两侧同时换到之前的修订记录前一修订版后一修订版 | 前一修订版 | ||
| edastudy:tessent:drc [2024/07/18 09:24] – [1.1 C1] user01 | edastudy:tessent:drc [2024/07/18 09:42] (当前版本) – [1.1 C1] user01 | ||
|---|---|---|---|
| 行 5: | 行 5: | ||
| ==== - C1 ==== | ==== - C1 ==== | ||
| - | When all clocks are at their off state as defined with the add_clocks command, all clock inputs (including sets and resets) of scan and non-scan cells must be at their off state. For non-scan cell violations, the tool converts these to <color # | + | When all clocks are at their off state as defined with the add_clocks command, all clock inputs (including sets and resets) of scan and non-scan cells must be at their off state. |
| + | For non-scan cell violations, the tool converts these to <color # | ||
| - | 注意： | + | 注意： 要定义成同步时钟。 |
edastudy/tessent/drc.1721265869.txt.gz · 最后更改: 2024/07/18 09:24 由 user01