edastudy:tessent:dft_signals
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edastudy:tessent:dft_signals [2024/09/03 20:51] – [4. test point insertion] user01 | edastudy:tessent:dft_signals [2024/10/07 09:03] (当前版本) – [3. connection cmd] user01 | ||
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- | ===== - connection cmd ===== | + | ===== - add_dft_control_points |
<code tcl> | <code tcl> | ||
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add_dft_control_points pllmux/s -dft_signal_source_name pll_bypass | add_dft_control_points pllmux/s -dft_signal_source_name pll_bypass | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
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+ | {{: | ||
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[-enable pin/ | [-enable pin/ | ||
</ | </ | ||
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+ | |||
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+ | ===== - add_dft_clock_mux ===== | ||
+ | 在pre-DC阶段之前添加CLOCK MUX,为了是时钟可控,测试时钟可选等等。 | ||
+ | |||
+ | <code tcl> | ||
+ | add_dft_clock_mux pin_port_net_spec -test_clock_source | ||
+ | [‑dft_signal_source_name | ||
+ | [-auto_uniquify] | ||
+ | </ | ||
+ | |||
+ | <code tcl> | ||
+ | add_clocks clka -period 6.7ns | ||
+ | > add_clocks vco_buf/Y ‑branch | ||
+ | > add_clocks clkb_buf/y ‑branch | ||
+ | > register_static_dft_signal_names alt_ref pll_bypass | ||
+ | > add_dft_clock_mux clkb -test_clock_source mem1/clk \ | ||
+ | -dft_signal_source_name all_test | ||
+ | > add_dft_clock_mux pll1/vco -test_clock_source pll1/ref \ | ||
+ | -dft_signal_source_name pll_bypass | ||
+ | > add_dft_clock_mux pll1/ref -test_clock_source clkb \ | ||
+ | -dft_signal_source_name alt_ref | ||
+ | > report_dft_clock_mux | ||
+ | // Dft clock muxes// =============== | ||
+ | // ---------- | ||
+ | // Node Test clock source | ||
+ | // ---------- | ||
+ | // ' | ||
+ | // ' | ||
+ | // ' | ||
+ | </ | ||
+ | |||
+ | {{: |
edastudy/tessent/dft_signals.1725367871.txt.gz · 最后更改: 2024/09/03 20:51 由 user01