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edastudy:tessent:dft_signals

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--- edastudy:tessent:dft_signals [2024/02/19 09:04] – [3. connection] zhangguo
+++ edastudy:tessent:dft_signals [2024/10/07 09:03] (当前版本) – [3. connection cmd] user01
@@ 行 116: / 行 116: @@
-===== - connection cmd =====
+===== - add_dft_control_points =====
 <code tcl>
@@ 行 127: / 行 127: @@
 add_dft_control_points pllmux/s -dft_signal_source_name pll_bypass
+{{:edastudy:tessent:pasted:20241007-090122.png?nolink}}
+{{:edastudy:tessent:pasted:20241007-090132.png?nolink}}
+{{:edastudy:tessent:pasted:20241007-090139.png?nolink}}
+{{:edastudy:tessent:pasted:20241007-090145.png?nolink}}
+{{:edastudy:tessent:pasted:20241007-090207.png?nolink}}
+{{:edastudy:tessent:pasted:20241007-090213.png?nolink}}
+===== - test point insertion =====
+<code tcl>
+Context: dft -test_points
+Mode: setup, analysis
+Specifies user-defined control points during test point insertion.
+Usage
+add_control_points -location pin/port_spec -type {AND | OR} [-clock clock_pin/port]
+[-enable enable_pin/port]
+</code>
+<code tcl>
+Context: dft -test_points
+Mode: setup, analysis
+Specifies user-defined observe points during test point insertion.
+Usage
+add_observe_points -location pin/port_spec
+[-clock pin/port_spec]
+[-enable pin/port_spec]
+</code>
+===== - add_dft_clock_mux =====
+在pre-DC阶段之前添加CLOCK MUX，为了是时钟可控，测试时钟可选等等。
+<code tcl>
+add_dft_clock_mux pin_port_net_spec -test_clock_source  test_clock_source_spec
+[‑dft_signal_source_name  dft_signal_source_name] [-inverse_dft_signal_source]
+[-auto_uniquify]
+</code>
+<code tcl>
+add_clocks clka -period 6.7ns
+> add_clocks vco_buf/Y ‑branch
+> add_clocks clkb_buf/y ‑branch
+> register_static_dft_signal_names alt_ref pll_bypass
+> add_dft_clock_mux clkb -test_clock_source mem1/clk \
+    -dft_signal_source_name all_test
+> add_dft_clock_mux pll1/vco -test_clock_source pll1/ref \
+    -dft_signal_source_name pll_bypass
+> add_dft_clock_mux pll1/ref -test_clock_source clkb \
+    -dft_signal_source_name alt_ref
+> report_dft_clock_mux
+// Dft clock muxes// ===============
+// ----------  ----------------- -------------------
+// Node Test   clock source      Control source name
+// ----------  ----------------- -------------------
+// 'clkb'      mem1/clk          all_test
+// 'pll1/vco'  pll1/ref          pll_bypass
+// 'pll1/ref'  clkb              alt_ref
+</code>
+{{:edastudy:tessent:pasted:20240904-081124.png?nolink}}

edastudy/tessent/dft_signals.1708304650.txt.gz · 最后更改: 2024/02/19 09:04 由 zhangguo