edastudy:tessent:atpg
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| 两侧同时换到之前的修订记录前一修订版后一修订版 | 前一修订版 | ||
| edastudy:tessent:atpg [2025/03/16 14:24] – [1.4 PR网表层次保持] user01 | edastudy:tessent:atpg [2026/07/06 19:14] (当前版本) – [3. X-bounding] user01 | ||
|---|---|---|---|
| 行 1: | 行 1: | ||
| ====== - atpg ====== | ====== - atpg ====== | ||
| + | |||
| + | ===== - LE TE概念 ===== | ||
| + | LE: Leading-Edge | ||
| + | TE: Trailing-Edge | ||
| + | |||
| + | {{: | ||
| + | |||
| + | {{: | ||
| + | |||
| ===== - Transition AC ===== | ===== - Transition AC ===== | ||
| 行 66: | 行 75: | ||
| 或者是多个OCC设置兼容模式 | 或者是多个OCC设置兼容模式 | ||
| + | 方式一：\\ | ||
| + | < | ||
| + | # 将同源或同频的 OCC 输出时钟分配到同一同步组 | ||
| + | add_synchronous_clock_group {clk1 clk1_p clk2 clk2_p} | ||
| + | # 如果是想把OCC输出也弄成一个group的话，这里只需要写occ的inst hier name | ||
| + | </ | ||
| + | |||
| + | 方式二：\\ | ||
| + | 将多个clk添加同一个clock_intercept_node上，它们会共享OCC的shift cgc，永远是同步输出capture clock。 | ||
| + | < | ||
| + | set occ [ add_config_element OCC/ | ||
| + | set_config_value clock_intercept_node -in $occ $clk | ||
| + | </ | ||
| + | |||
| + | 在ATPG时启用兼容时钟模式：\\ | ||
| + | set_clock_restriction domain_clock -compatible_clocks_between_loads on | ||
| + | |||
| + | report_synchronous_clock_groups | ||
| ====== - gen atpg pattern ====== | ====== - gen atpg pattern ====== | ||
| 行 106: | 行 133: | ||
| 让逻辑结合部分在shift阶段状态不变化, | 让逻辑结合部分在shift阶段状态不变化, | ||
| + | |||
| + | |||
| + | ====== - X-bounding ====== | ||
| + | 如果报 | ||
| + | < | ||
| + | // Warning: Could not identify the data path input for the library cell containing | ||
| + | // the memory element at /dff115/D (382.4). X-bounding logic cannot be inserted in | ||
| + | // the scan path so this is a fatal error. This could be caused by missing | ||
| + | // pin constraints and/or scan_enable connections. (XB2-1) | ||
| + | </ | ||
| + | 一个解法是给对应的register cell换成带scan cell的，要么把它的SE悬空，要么把它case为1，即能在它前面正常插入x-bounding. | ||
edastudy/tessent/atpg.1742106288.txt.gz · 最后更改: 2025/03/16 14:24 由 user01