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--- edastudy:bscan:pad_lib [2024/06/16 08:49] – [6.3 od inv pull1 pad] user01
+++ edastudy:bscan:pad_lib [2025/05/24 21:05] (当前版本) – [7. AC diff input pad] user01
@@ 行 208: / 行 208: @@
+===== - AC diff output pad =====
+{{:edastudy:bscan:pasted:20250524-204325.png?nolink}}
+===== - AC diff input pad =====
+{{:edastudy:bscan:pasted:20250524-204357.png?nolink}}
+Test Receiver Example\\
+{{:edastudy:bscan:pasted:20250524-204418.png?nolink}}
+initClk电路：
+{{:edastudy:bscan:pasted:20250524-210348.png?nolink}}
+在EXTEST模式下，进行DC测试，在capture DR的下降沿初始化TestData值\\
+在AC EXTEST(即PULSE/TRAIN)模式下，在EXIT1-DR/EXIT2-DR初始化TestData值
 ===== - OD OS psd =====
@@ 行 338: / 行 355: @@
      primitive = _pull mlc_pull_1 (1, PAD);
-     primitive = _inv   mlc_inv_1  (D0, DOinv);
+     primitive = _inv   mlc_inv_1  (DO, DOinv);
-     primitive = _tsh mlc_tsh_1 (D0inv, DO, PAD);
+     primitive = _tsh mlc_tsh_1 (DOinv, DO, PAD);
    )
 )
@@ 行 382: / 行 399: @@
      primitive = _buf mlc_buf_1 (PAD, DI);
-     primitive = _inv   mlc_inv_1  (D0, DOinv);
+     primitive = _inv   mlc_inv_1  (DO, DOinv);
-     primitive = _tsh mlc_tsh_1 (D0inv, DO, PAD);
+     primitive = _tsh mlc_tsh_1 (DOinv, DO, PAD);
    )
 )
@@ 行 393: / 行 410: @@
 input   DO;
 inout   PAD;
 assign PAD = (DO == 1'b1) ? 1'b0 : 1'bz;

edastudy/bscan/pad_lib.1718498969.txt.gz · 最后更改: 2024/06/16 08:49 由 user01