edastudy:bscan:bscan学习
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| edastudy:bscan:bscan学习 [2025/05/23 09:54] – [表] user01 | edastudy:bscan:bscan学习 [2026/10/15 21:29] (当前版本) – 外部编辑 127.0.0.1 | ||
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| - | ====== | + | # BSCAN学习 |
| 参考IEEE.Std.1149.6-2003.pdf | 参考IEEE.Std.1149.6-2003.pdf | ||
| - | ===== - JTAG TAP FSM ===== | + | ## - JTAG TAP FSM |
| - | {{: | + | ![: |
| - | ===== - tessent bscan interface | + | ## - tessent bscan interface |
| 左侧是开了ac_control选项，右侧没有开，生成出来bscan interface模块的区别： | 左侧是开了ac_control选项，右侧没有开，生成出来bscan interface模块的区别： | ||
| - | {{: | + | ![: |
| + | |||
| + | ## - AC test signal | ||
| + | |||
| + | | tessent tap | SNPS PHY信号 | 说明 | | ||
| + | | --- | --- | --- | | ||
| + | | to_bscan_ac_mode_en | bs_acmode | 表示EXTEST_PULSE or EXTEST_TRAIN有效，处于BSCAN AC测试模式 | | ||
| + | | to_bscan_ac_signal | bs_actest | 在JTAG IDLE状态，测试信号拉高（EXTEST_PULSE模式）, | ||
| + | | to_bscan_ac_init_clock0 | bs_rx_init | | | ||
| + | | to_bscan_ac_init_clock1 | | ~to_bscan_ac_init_clock0 | | ||
| + | |||
| + | initclk\ | ||
| + | ![: | ||
| + | |||
| + | ![: | ||
| - | ===== - AC test signal ===== | + | ![: |
| - | ^ tessent tap ^ SNPS PHY信号 | + | ac test signal, 只在RTI模式下数据才有效， |
| - | | to_bscan_ac_mode_en | + | ![: |
| - | | to_bscan_ac_signal | + | |
| - | | to_bscan_ac_init_clock0 | + | |
| - | | to_bscan_ac_init_clock1 | + | |
| - | {{: | ||
| - | < | + | ``` |
| ACMODE = EXTEST_TRAIN | EXTEST_PULSE; | ACMODE = EXTEST_TRAIN | EXTEST_PULSE; | ||
| 行 36: | 行 45: | ||
| ac_init_clk_EXTEST = SDR & bscan_select; | ac_init_clk_EXTEST = SDR & bscan_select; | ||
| ac_init_clk_EXTEST_TRAIN_OR_PULSE = (E1DR | E2DR) & ACMODE; | ac_init_clk_EXTEST_TRAIN_OR_PULSE = (E1DR | E2DR) & ACMODE; | ||
| - | </ | + | ``` |
| - | ===== - Input test receivers | + | |
| + | ## - Input test receivers | ||
| 接收器在接收的时候分为DC Coupled和AC Coupled。 | 接收器在接收的时候分为DC Coupled和AC Coupled。 | ||
| - | {{: | + | ![: |
| - | 所述接收器，应该在capture-DR状态时能采样到一个有效的值，如果不能采到有效值，应该会有一个initial value被采到。 | + | **EXTEST测试时，在capture-DR状态，TCK下降沿，接收器给一个初始值** |
| - | {{: | + | ![: |
| - | 就如下图一样，capture-DR状态采到有效值或者initial value | + | **AC EXTEST测试时，在TCK上升沿，updata |
| - | {{: | + | ![: |
| - | 所以接收器在Exti1-DR或者Exit2-DR (其实就是在Update状态之前先给个initial值)的时候可以把sample register给个initial state(比如说固定为0)，接收器示范电路如下： | + | 接收器示范电路如下： |
| - | **下图对应s家phy bs_rx_init信号** | ||
| - | {{: | + | ![: |
| - | **下图对应s家phy bs_actest** | ||
| - | |||
| - | {{: | ||
| - | ===== - Output drivers ===== | ||
| + | ![: | ||
| + | ## - Output drivers | ||
| output driver不会太特殊 | output driver不会太特殊 | ||
| - | {{: | + | ![: |
| - | {{: | + | ![: |
| - | ===== - instruction | + | ## - instruction |
| - | ==== - EXTEST_PULSE | + | ### - EXTEST_PULSE |
| - | {{: | + | ![: |
| - | ==== - EXTEST_TRAIN | + | ### - EXTEST_TRAIN |
| - | {{: | + | ![: |
| - | ===== - clockdr & updatedr | + | ## - clockdr & updatedr |
| - | < | + | ```verilog |
| clockir = ((pstate == capture_IR) || (pstate == shift_IR)) ? tck : 1'b1; | clockir = ((pstate == capture_IR) || (pstate == shift_IR)) ? tck : 1'b1; | ||
| clockdr = ((pstate == capture_DR) || (pstate == shift_DR)) ? tck : 1'b1; | clockdr = ((pstate == capture_DR) || (pstate == shift_DR)) ? tck : 1'b1; | ||
| - | </ | + | ``` |
| 在capture状态capture数据，在shift状态，shift数据。 | 在capture状态capture数据，在shift状态，shift数据。 | ||
| - | {{: | + | ![: |
| - | ===== - tessent BC cell ===== | + | ## - tessent BC cell |
| ref: bsda_ref.pdf | ref: bsda_ref.pdf | ||
| - | ==== - BC_1 ==== | + | ### - BC_1 |
| - | {{: | + | ![: |
| - | ==== - BC_2 ==== | + | ### - BC_2 |
| - | {{: | + | ![: |
| - | ==== - BC_2_A | + | ### - BC_2_A |
| - | {{: | + | ![: |
| - | ==== - BC_2_A_EXT | + | ### - BC_2_A_EXT |
| - | {{: | + | ![: |
| - | ==== - BC_2_B | + | ### - BC_2_B |
| - | {{: | + | ![: |
| - | ==== - BC_3 ==== | + | ### - BC_3 |
| - | {{: | + | ![: |
| - | ==== - BC_4 ==== | + | ### - BC_4 |
| - | {{: | + | ![: |
| - | ==== - BC_5 ==== | + | ### - BC_5 |
| - | {{: | + | ![: |
| - | ==== - BC_7 ==== | + | ### - BC_7 |
| - | {{: | + | ![: |
| - | ==== - BC_7_LOW | + | ### - BC_7_LOW |
| - | {{: | + | ![: |
| - | ==== - BC_8 ==== | + | ### - BC_8 |
| - | {{: | + | ![: |
| - | ==== - BC_9 ==== | + | ### - BC_9 |
| - | {{: | + | ![: |
| - | ==== - BC_10 ==== | + | ### - BC_10 |
| - | {{: | + | ![: |
| - | ===== - tessent AC cell ===== | + | ## - tessent AC cell |
| ref: bsda_ref.pdf | ref: bsda_ref.pdf | ||
| - | ==== - AC_1 ==== | + | ### - AC_1 |
| - | {{: | + | ![: |
| - | ==== - AC_2 ==== | + | ### - AC_2 |
| - | {{: | + | ![: |
| - | ==== - AC_7 ==== | + | ### - AC_7 |
| - | {{: | + | ![: |
| - | ==== - AC_7_LOW | + | ### - AC_7_LOW |
| - | {{: | + | ![: |
| - | ==== - AC_8 ==== | + | ### - AC_8 |
| - | {{: | + | ![: |
| - | ==== - AC_9 ==== | + | ### - AC_9 |
| - | {{: | + | ![: |
| - | ==== - AC_10 ==== | + | ### - AC_10 |
| - | {{: | + | ![: |
| - | ===== - IEEE 1149.1 BSCAN BC cell ===== | + | ## - IEEE 1149.1 BSCAN BC cell |
| * BC_1, input cell, control cell, capture misson input | * BC_1, input cell, control cell, capture misson input | ||
| * BC_2, input cell, control cell, capture misson output | * BC_2, input cell, control cell, capture misson output | ||
| 行 178: | 行 185: | ||
| - | ==== - BC_1 ==== | + | ### - BC_1 |
| **mode** | **mode** | ||
| - | {{: | + | ![: |
| - | {{: | + | ![: |
| - | ==== - BC_2 ==== | + | ### - BC_2 |
| - | {{: | + | ![: |
| - | {{: | + | ![: |
| - | ==== - BC_3 ==== | + | ### - BC_3 |
| - | <color # | + | <span style=" |
| - | {{: | + | ![: |
| - | ==== - BC_4 ==== | + | ### - BC_4 |
| - | {{: | + | ![: |
| - | ==== - BC_5 ==== | + | ### - BC_5 |
| + | ![: | ||
| - | {{: | + | ![: |
| - | {{: | ||
| + | ### - BC_7 | ||
| + | ![: | ||
| - | ==== - BC_7 ==== | + | ![: |
| - | {{: | + | |
| - | {{: | ||
| - | + | ### - BC_8 | |
| - | ==== - BC_8 ==== | + | |
| **mode** | **mode** | ||
| - | {{: | + | ![: |
| - | {{: | + | ![: |
| **bc_2 control + bc_8** | **bc_2 control + bc_8** | ||
| - | {{: | + | ![: |
| - | ==== - BC_9 ==== | + | ### - BC_9 |
| - | {{: | + | ![: |
| - | {{: | + | ![: |
| - | ==== - BC_10 ==== | + | ### - BC_10 |
| - | {{: | + | ![: |
| - | {{: | + | ![: |
| - | ===== - BSCAN AC cell ===== | + | ## - BSCAN AC cell |
| * AC_SelX, 控制选择AC/ | * AC_SelX, 控制选择AC/ | ||
| * AC_SelU, 控制选择AC/ | * AC_SelU, 控制选择AC/ | ||
| 行 247: | 行 252: | ||
| * AC_10, self-monitor output cell; capture PAD output only | * AC_10, self-monitor output cell; capture PAD output only | ||
| - | |||
| - | ^ ^ mode 1 ^ mode 2 ^ mode 3 ^ mode 4 ^ mode 5 ^ | ||
| - | | EXTEST | ||
| - | | PRELOAD | ||
| - | | SAMPLE | ||
| - | | INTEST | ||
| - | | RUNBIST | ||
| - | | CLAMP | 1 | X | 1 | X | 1 | | ||
| - | | HIGHZ | X | X | 0 | X | X | | ||
| - | | NOTES:\\ 1. EXTEST inluce EXTEST, EXTEST_PLUSE, | ||
| - | ==== - AC_SelX ==== | + | | | mode 1 | mode 2 | mode 3 | mode 4 | mode 5 | |
| - | {{:edastudy: | + | | --- | --- | --- | --- | --- | --- | |
| + | | EXTEST | 1 | 0 | 1 | 1 | 1 | | ||
| + | | PRELOAD | 0 | 0 | 1 | X | 0 | | ||
| + | | SAMPLE | 0 | 0 | 1 | 0 | 0 | | ||
| + | | INTEST | 0 | 1 | 0 | 0 | 1 | | ||
| + | | RUNBIST | X | X | 0 | X | 1 | | ||
| + | | CLAMP | 1 | X | 1 | X | 1 | | ||
| + | | HIGHZ | X | X | 0 | X | X | | ||
| + | | NOTES: 1. EXTEST inluce EXTEST, EXTEST_PLUSE, | ||
| - | ==== - AC_SelU ==== | ||
| - | {{: | ||
| - | ==== - AC_1 ==== | ||
| - | {{: | ||
| - | ==== - AC_2 ==== | + | ### - AC_SelX |
| - | {{: | + | ![: |
| - | ==== - AC_7 ==== | + | ### - AC_SelU |
| - | {{: | + | ![: |
| + | ### - AC_1 | ||
| + | ![: | ||
| - | ==== - AC_8 ==== | + | ### - AC_2 |
| - | {{: | + | ![: |
| - | ==== - AC_9 ==== | + | ### - AC_7 |
| - | {{: | + | ![: |
| - | ==== - AC_10 ==== | + | ### - AC_8 |
| + | ![: | ||
| - | {{: | + | ### - AC_9 |
| + | ![: | ||
| - | ===== - BSCAN指令 ===== | + | ### - AC_10 |
| + | ![: | ||
| - | ==== - SAMPLE | + | ## - BSCAN指令 |
| + | ### - SAMPLE | ||
| 只sample采样 capture pin input & output值，而不能影响其input pin到内部逻辑值和output pin到PAD的状态。 | 只sample采样 capture pin input & output值，而不能影响其input pin到内部逻辑值和output pin到PAD的状态。 | ||
| - | ==== - PRELOAD | + | ### - PRELOAD |
| 主要用来更新update DR的值，这个值在后面的测试指令作用下，将会直接被驱动到output PAD脚；如果值没有初始化，将不确定输出的是什么值。 | 主要用来更新update DR的值，这个值在后面的测试指令作用下，将会直接被驱动到output PAD脚；如果值没有初始化，将不确定输出的是什么值。 | ||
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