Writing /share/Web/wiki/data/cache/f/f92bc2d80df221635891ecfff7a5f989.metadata failed
协议学习:amba:axi4_lite
差别
这里会显示出您选择的修订版和当前版本之间的差别。
| 两侧同时换到之前的修订记录前一修订版 | |||
| 协议学习:amba:axi4_lite [2024/12/26 10:32] – 移除 - 外部编辑 (Unknown date) 127.0.0.1 | 协议学习:amba:axi4_lite [2024/12/26 10:32] (当前版本) – ↷ 页面协议学习:axi:axi4_lite被移动至协议学习:amba:axi4_lite user01 | ||
|---|---|---|---|
| 行 1: | 行 1: | ||
| + | ====== axi4-lite ====== | ||
| + | < | ||
| + | AXI4 signals not supported in AXI4-Lite | ||
| + | |||
| + | The AXI4-Lite interface does not support the following signals: | ||
| + | |||
| + | AWLEN, ARLEN | ||
| + | The burst length is defined to be 1, equivalent to an AxLEN value of zero. | ||
| + | |||
| + | AWSIZE, ARSIZE | ||
| + | All accesses are defined to be the width of the data bus. | ||
| + | Note | ||
| + | AXI4-Lite requires a fixed data bus width of either 32-bit or 64-bit. | ||
| + | |||
| + | AWBURST, ARBURST | ||
| + | The burst type has no meaning because the burst length is 1. | ||
| + | |||
| + | AWLOCK, ARLOCK | ||
| + | All accesses are defined as Normal accesses, equivalent to an AxLOCK value of zero. | ||
| + | |||
| + | AWCACHE, ARCACHE | ||
| + | All accesses are defined as Non-modifiable, | ||
| + | value of 0b0000. | ||
| + | |||
| + | WLAST, RLAST | ||
| + | All bursts are defined to be of length 1, equivalent to a WLAST or RLAST value of 1 | ||
| + | </ | ||