#! /bin/sh
#\
exec tessent -shell -log logfiles/$0.log -replace -dofile "$0"  -arguments ${1+"$@"}
#
# Set the context to insert DFT into RTL-level design
set_context dft -rtl -design_id rtl1
# Use dft_cell_selection that is part of the library
read_cell_library ../../../library/standard_cells/tessent/adk.tcelllib

# Set the location of the TSDB. Default is the current working directory.
set_tsdb_output_directory ../tsdb_outdir_new

# Read the design
read_verilog  "../rtl/carrier_nco.v" 
read_verilog  "../rtl/accumulator.v" 
read_verilog  "../rtl/code_nco.v" 
read_verilog  "../rtl/lpm_counter.v" 
read_verilog  "../rtl/time_base.v" 
read_verilog  "../rtl/carrier_mixer.v" 
read_verilog  "../rtl/code_gen.v" 
read_verilog  "../rtl/epoch_counter.v" 
read_verilog  "../rtl/lpm_counter_ud.v" 
read_verilog  "../rtl/lpm_shiftreg.v" 
read_verilog  "../rtl/tracking_channel.v" 
read_verilog  "../tsdb_outdir/dft_inserted_designs/gps_baseband_rtl1.dft_inserted_design/modified_rtl_files/gps_baseband.v" 
read_verilog  "../tsdb_outdir/instruments/gps_baseband_rtl1_ijtag.instrument/gps_baseband_rtl1_tessent_sib_1.v" 
read_verilog  "../tsdb_outdir/instruments/gps_baseband_rtl1_ijtag.instrument/gps_baseband_rtl1_tessent_sib_2.v" 
read_verilog  "../tsdb_outdir/instruments/gps_baseband_rtl1_ijtag.instrument/gps_baseband_rtl1_tessent_tdr_sri_ctrl.v" 
read_verilog  "../tsdb_outdir/instruments/gps_baseband_rtl1_ssn.instrument/gps_baseband_rtl1_tessent_ssn_pipe_w2_1.v" 
read_verilog  "../tsdb_outdir/instruments/gps_baseband_rtl1_ssn.instrument/gps_baseband_rtl1_tessent_ssn_scan_host_1.v" 
read_verilog  "../tsdb_outdir/instruments/gps_baseband_rtl1_occ.instrument/gps_baseband_rtl1_tessent_occ.v" 
read_verilog  "../tsdb_outdir/instruments/gps_baseband_rtl1_edt.instrument/gps_baseband_rtl1_tessent_edt_c1_int.v" 
read_verilog  "../tsdb_outdir/instruments/gps_baseband_rtl1_edt.instrument/gps_baseband_rtl1_tessent_edt_c1_ext.v" 
read_verilog  "../tsdb_outdir/instruments/gps_baseband_rtl1_edt.instrument/gps_baseband_rtl1_tessent_edt_c1_int_tdr.v" 
read_verilog  "../tsdb_outdir/instruments/gps_baseband_rtl1_edt.instrument/gps_baseband_rtl1_tessent_edt_c1_ext_tdr.v" 
read_verilog  "../tsdb_outdir/instruments/gps_baseband_rtl1_edt.instrument/gps_baseband_rtl1_edt_channel_out_mux_4x1_1.v" 

read_verilog ./mpu.v


read_icl ../tsdb_outdir/instruments/gps_baseband_rtl1_occ.instrument/gps_baseband_rtl1_tessent_occ.icl
read_icl ../tsdb_outdir/instruments/gps_baseband_rtl1_ssn.instrument/gps_baseband_rtl1_tessent_ssn_pipe_w2_1.icl
read_icl ../tsdb_outdir/instruments/gps_baseband_rtl1_ssn.instrument/gps_baseband_rtl1_tessent_ssn_scan_host_1.icl
read_icl ../tsdb_outdir/instruments/gps_baseband_rtl1_ijtag.instrument/gps_baseband_rtl1_tessent_tdr_sri_ctrl.icl
read_icl ../tsdb_outdir/instruments/gps_baseband_rtl1_ijtag.instrument/gps_baseband_rtl1_tessent_sib_1.icl
read_icl ../tsdb_outdir/instruments/gps_baseband_rtl1_ijtag.instrument/gps_baseband_rtl1_tessent_sib_2.icl
read_icl ../tsdb_outdir/instruments/gps_baseband_rtl1_edt.instrument/gps_baseband_rtl1_tessent_edt_c1_int.icl
read_icl ../tsdb_outdir/instruments/gps_baseband_rtl1_edt.instrument/gps_baseband_rtl1_tessent_edt_c1_ext.icl
read_icl ../tsdb_outdir/instruments/gps_baseband_rtl1_edt.instrument/gps_baseband_rtl1_tessent_edt_c1_int_tdr.icl
read_icl ../tsdb_outdir/instruments/gps_baseband_rtl1_edt.instrument/gps_baseband_rtl1_tessent_edt_c1_ext_tdr.icl

read_core_descriptions ../tsdb_outdir/instruments/gps_baseband_rtl1_ssn.instrument/gps_baseband_rtl1_tessent_ssn_scan_host_1.tcd

#set_current_design gps_baseband
set_current_design mpu

# Set the design level as physical_block
#set_design_level physical_block
set_design_level chip

add_icl_ssn_datapaths 2
#set_icl_ssn_datapath_ports -name 1 \
    -clock_inputs P_T8 -bus_data_inputs {P_T10 P_T9} -bus_data_outputs {P_T0 P_T1}
set_icl_ssn_datapath_ports -name 2 \
    -clock_inputs P_T8 -bus_data_inputs {P_T9 P_T10} -bus_data_outputs {P_T1 P_T0}


check_design_rules

extract_icl


get_icl_ssn_datapath_list 
get_icl_ssn_datapath_ports -name 2




# Generate patterns. Use the variable to update it if needed.
set spec [create_pattern_specification]

# Report the pattern configuration wrappers created
report_config_data $spec

# Validate pattern specification
process_pattern_specification

# Run Simulation
set_simulation_library_sources -v ../../../library/standard_cells/verilog/adk.v
#run_testbench_simulations
run_testbench_simulations -simulator vcs \
    -compilation_options "+define+debussy" \
    -simulator_options "-debug_access+all -debug_region=cell+lib -kdb -lca"

check_testbench_simulations -report_status

exit